Many controller exist, in particular stand alone controllers, that comprise a large memory that is not directly accessible by a processor due to constraints in address size of an associated interface. For example, Ethernet controllers, in particular stand alone Ethernet Controllers, are designed to serve as an Ethernet network interface for any type of microprocessor or microcontroller. Such a controller can have a fairly large memory and may include a dedicated interface such as a serial peripheral interface (SPI) bus. In some embodiments, such an Ethernet controller may also be integrated in a microcontroller using the SPI bus or any other capable interface connection. In case of an Ethernet controller, the controller handles all communication protocols and comprises a large buffer for intermediate storage of incoming and outgoing messages. A microcontroller or microprocessor may then communicate and control the Ethernet controller via the interface. The stand alone or an integrated Ethernet controller handles coordination of incoming and outgoing data packets as well as packet filtering. It may further comprise an internal direct memory access (DMA) module for fast data throughput and hardware assisted checksum calculation. The communication of an Ethernet controller with a microcontroller or microprocessor can be established interrupt or polling driven.
As stated above, the buffer incorporated in this type of controllers is relatively large and, therefore, cannot be directly addressed, due to address size limitations of the communication protocols of the respective interface. Hence, the buffer is generally accessed through a windowed interface via a set of control registers. Such a set of control registers comprises a register for data to be written or read and at least one pointer register containing the physical read or write address of the buffer. This accessing scheme however may cause a bottleneck in present Ethernet controllers in particular for operations that often switch between read and write access or between different tasks accessing the Ethernet buffer that make it necessary every time a switch occurs to save the content of the pointer registers.